Combined altitude and underground real-time SER characterization of CMOS technologies on the ASTEP-LSM platform

• Published in: 2009 IEEE International Conference on IC Design and Technology pp. 113 - 120
• Main Authors: Autran, J.L., Roche, P., Sauze, S., Gasiot, G., Munteanu, D., Loaiza, P., Zampaolo, M., Borel, J., Rozov, S., Yakushev, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: accelerated tests; alpha contamination; atmospheric neutrons; Circuit testing; CMOS technology; Contamination; Cosmic rays; Impurities; Laboratories; Microelectronics; Nanostructured materials; neutron-induced SER; Neutrons; Performance evaluation; real-time testing; SER simulation; Single-Event Rate (SER); static memory; terrestrial radiation environment
• ISBN: 1424429331; 9781424429332
• ISSN: 2381-3555
• DOI: 10.1109/ICICDT.2009.5166277

This work surveys our 2005-2009 experimental contributions to develop a combined altitude and underground test platform devoted to the soft-error rate (SER) characterization of deca-nanometer CMOS technologies. The platform currently involves two complementary sites to separate the component of the SER induced by the cosmic rays from that caused by on-chip radioactive impurities: the Altitude SEE Test European Platform (ASTEP) located at the altitude of 2252 m on the Plateau de Bure (French south Alps) and the Underground Laboratory of Modane (LSM) in the Frejus tunnel under 1700 m of rock (4800 meters water equivalent). These two sites have both dedicated instrumentations for neutron monitoring and circuit SER characterization. Long-duration real-time experimental measurements obtained using several gigabits of SRAMs manufactured in CMOS 130 nm and 65 nm technologies are reported and analyzed.