An efficient implementation of GLCM algorithm in FPGA

This paper presents hardware (HW) architecture for fast parallel computation of Gray Level Co-occurrence Matrix (GLCM) in high throughput image analysis applications. GLCM has proven to be a powerful basis for use in texture classification. Various textural parameters calculated from the GLCM help u...

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Bibliographic Details
Published in2018 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC) pp. 147 - 152
Main Authors Ben Atitallah, M. A., Kachouri, R., Kammoun, M., Mnif, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2018
Subjects
Acceleration
Computer architecture
Feature extraction
Field programmable gate arrays
FPGA
Haralick's texture feature
Hardware
Hardware Implementation
Image analysis applications
Latency number
Optimization
Parallel computation
Symmetric Co-occurrence matrix (GLCM)
Vivado HLS
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DOI10.1109/IINTEC.2018.8695275

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Summary:This paper presents hardware (HW) architecture for fast parallel computation of Gray Level Co-occurrence Matrix (GLCM) in high throughput image analysis applications. GLCM has proven to be a powerful basis for use in texture classification. Various textural parameters calculated from the GLCM help understand the details about the overall image content. However, the calculation of GLCM is very computationally intensive. In this paper, an FPGA accelerator for fast calculation of GLCM is designed and implemented. We propose an FPGA-based architecture for parallel computation of symmetric co-occurrence matrices. This architecture was implemented on a Xilinx Zedboard and Virtex 5 FPGAs using Vivado HLS. The performance is then compared against other implementations. The validation results show an optimization on the order of 33% in latency number by contribution to the literature implementation.
DOI:10.1109/IINTEC.2018.8695275