Comparison of various strategies of implementation of the algorithm of encryption AES on FPGA

• Published in: 2006 IEEE International Symposium on Industrial Electronics Vol. 4; pp. 3276 - 3280
• Main Authors: Perez, O., Berviller, Y., Tanougast, C., Weber, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2006
• Subjects: Circuit faults; Computer architecture; Costs; Cryptography; Data security; Encoding; Field programmable gate arrays; Hardware; Protection; Safety
• ISBN: 9781424404964; 1424404967
• ISSN: 2163-5137
• DOI: 10.1109/ISIE.2006.296142

The data security is a significant subject for which various solutions algorithms were proposed. In 2001, advanced encryption system (AES) was accepted like a standard FIPS. AES is a symmetrical algorithm of encoding intended to replace DES which had already shown certain faults of safety in the data protection. Since then, of many achievements on hardware and software were proposed by combining various architectures. The throughput reached go from 20 Mbps to 70 Gbps according to technology and architecture used. This article presents an architecture which can be implemented on the FPGA Xilinx XC2V6000, by applying dynamic reconfiguration and reaching a speed of execution of 43 Gbps. This architecture employs only 2xxx CLB' S allowing a considerable economy of the resources