A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems

• Published in: Applied Reconfigurable Computing. Architectures, Tools, and Applications Vol. 10824; pp. 511 - 522
• Main Authors: Ferreira, Mário Lopes, Ferreira, João Canas, Huebner, Michael
• Format: Book Chapter
• Language: English
• Published: Switzerland Springer International Publishing AG 2018; Springer International Publishing
• Series: Lecture Notes in Computer Science
• Subjects: Baseband processing; Dynamic frequency scaling; FPGA; OFDM modulator; Parallel-pipelined architecture
• ISBN: 3319788892; 9783319788890
• ISSN: 0302-9743; 1611-3349
• DOI: 10.1007/978-3-319-78890-6_41

5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible.