Mixed-precision weights network for field-programmable gate array

• Published in: PLOS ONE Vol. 16; no. 5; p. e0251329
• Main Authors: Fuengfusin, Ninnart, Tamukoh, Hakaru
• Format: Journal Article
• Language: English
• Published: United States Public Library of Science (PLoS) 10.05.2021; Public Library of Science
• Subjects: Accuracy; Algorithms; Analysis; Artificial neural networks; Bayes Theorem; Biology and Life Sciences; Computer and Information Sciences; Design; Digital integrated circuits; Drafting software; Editing; Engineering and Technology; Field programmable gate arrays; Graduate schools; Graduate studies; Hardware; Image processing; Image segmentation; Language; Life sciences; Medicine; Neural networks; Neural Networks, Computer; Object recognition; Pattern Recognition, Automated; Physical Sciences; Q; R; Research and Analysis Methods; Research facilities; Science; Searching; Signal Processing, Computer-Assisted; Social Sciences; Software; Sparsity; Systems engineering; Technology; Time Factors; Japan
• ISSN: 1932-6203; 1932-6203
• DOI: 10.1371/journal.pone.0251329

In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {−1,1}, ternary {−1,0,1}, and 32-bit floating-point. We further developed the MPWN from both software and hardware aspects. From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets. We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight space combinations. From the hardware aspect, we proposed XOR signed-bits to explore floating-point and binary weight spaces in the MPWN. XOR signed-bits is an efficient implementation equivalent to multiplication of floating-point and binary weight spaces. Using the concept from XOR signed bits, we also provide a ternary bitwise operation that is an efficient implementation equivalent to the multiplication of floating-point and ternary weight space. To demonstrate the compatibility of the MPWN with hardware implementation, we synthesized and implemented the MPWN in a field-programmable gate array using high-level synthesis. Our proposed MPWN implementation utilized up to 1.68-4.89 times less hardware resources depending on the type of resources than a conventional 32-bit floating-point model. In addition, our implementation reduced the latency up to 31.55 times compared to 32-bit floating-point model without optimizations.