Efficient FPGA Implementation of Visual Cryptography Using AES Algorithm and Share Generation Technique

• Published in: International Journal of Computational and Experimental Science and Engineering Vol. 11; no. 3
• Main Authors: P J, Sapna, Sudha K L, Deepa N P, K N Pushpalatha
• Format: Journal Article
• Language: English
• Published: 23.06.2025
• ISSN: 2149-9144; 2149-9144
• DOI: 10.22399/ijcesen.3070

Visual Cryptography is the latest secure communication technique where the secured data is always in the form of an image from which a finite number of shares are generated using a mathematical model. At the receiver side, the secret image is generated from these shares using a reverse mathematical approach. In this Article, Efficient FPGA Implementation of Visual Cryptography using AES Algorithm and Share Generation Technique is proposed. To increase security, AES algorithm is used for encoding, and is further subjected to share generation, the entire architectural level is designed to achieve optimum utilization without affecting the reconstruction quality, which is then coded using VHDL language and implemented on Zybo Z7-10 FPGA board. The comparison results show that the proposed technique is better in terms of both hardware parameters and reconstructed image quality.