Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications

• Published in: PloS one Vol. 12; no. 5; p. e0176214
• Main Authors: Hossain, Md Selim, Saeedi, Ehsan, Kong, Yinan
• Format: Journal Article
• Language: English
• Published: United States Public Library of Science 01.05.2017; Public Library of Science (PLoS)
• Subjects: Acidity; Algorithms; Architecture; Arithmetic; Chess; Circuit design; Computer and Information Sciences; Computer architecture; Computer Security - instrumentation; Computer systems; Computers; Coordinates; Cryptography; Customization; Customizing; Data processing; Data security; Design; Design and construction; Devices; Embedding; Engineering; Engineering research; Fabrication; Field programmable gate arrays; Hardware; High speed; Integrated circuits; Latency; Mathematical analysis; Mathematics; Microprocessors; Multimedia; Multiplication; Optimization; Physical Sciences; Privacy; Processor architectures; Programmable logic arrays; Protein kinase C; Protocol; Protocol (computers); Remote sensors; Research and Analysis Methods; Security; Social Sciences; Sodium channels; Technology; United States; United States Government Agencies; Upgrading; Very large scale integration; Wireless networks
• ISSN: 1932-6203; 1932-6203
• DOI: 10.1371/journal.pone.0176214

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance ([Formula: see text]) and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature.