一款低噪声八相位锁相环设计

基于宽频率范围数字系统的需求，在0．13μm工艺下设计了一款宽输出范围、低抖动八相位锁相环。首先通过数学建模优化环路带宽，在系统级减小环路噪声；在振荡器中引入了前馈传输管单元以提高振荡频率并降低振荡器相位噪声；最后利用具有伪静态结构的D触发器来降低鉴相器和分频器的功耗并提高其抗噪声能力。仿真结果表明，VCO输出频率在1．2GHz时相位噪声为～95dBc／Hz@lMHz，FOM功耗为4．5PJ@2GHZ。...

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Bibliographic Details
Published in计算机工程与科学 Vol. 38; no. 1; pp. 28 - 32
Main Author 宋意良 袁珩洲 刘尧 梁斌 郭阳
Format Journal Article
LanguageChinese
Published 国防科学技术大学计算机学院,湖南长沙,410073 2016
Subjects
低相位噪声
多相位
宽输出范围
环路带宽
电荷泵锁相环
环路带宽
多相位
CPPLL
multiphase
low phase noise
wide output range
低相位噪声
loop bandwidth
电荷泵锁相环
宽输出范围
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ISSN1007-130X
DOI10.3969/j.issn.1007-130X.2016.01.004

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Summary:基于宽频率范围数字系统的需求，在0．13μm工艺下设计了一款宽输出范围、低抖动八相位锁相环。首先通过数学建模优化环路带宽，在系统级减小环路噪声；在振荡器中引入了前馈传输管单元以提高振荡频率并降低振荡器相位噪声；最后利用具有伪静态结构的D触发器来降低鉴相器和分频器的功耗并提高其抗噪声能力。仿真结果表明，VCO输出频率在1．2GHz时相位噪声为～95dBc／Hz@lMHz，FOM功耗为4．5PJ@2GHZ。
Bibliography:To meet the needs of a wide frequency range of digital systems, we design a wide output range, low phase jitter eight-phase lock loop in the 0.13/,m process. We first optimize the loop band- width through mathematical modeling to reduce the loop noise at the system level. A feed-forward trans- fer tube unit is introduced to increase the oscillation frequency and to reduce the oscillator＇s phase noise. Finally, we leverage the D flip-flop, which has a pseudo-static structure, to reduce the power consump- tion of phase detectors and dividers, and maximize the noise immunity. Simulation results show that the phase noise is -95 dBe/Hz@l MHz,FOM power is 4.5 PJ@2 GHz when the VCO output frequency is 1.2 GHz.
43-1258/TP
CPPLL ;loop bandwidth ; low phase noise ; multiphase ; wide output range
SONG Yi-liang, YUAN Heng-zhou, LIU Yao, LIANG Bin, GUO Yang （College of Computer, National University of Defense Technology,Changsha 410073, China）
ISSN:1007-130X
DOI:10.3969/j.issn.1007-130X.2016.01.004