以访存为中心的阵列众核处理器核心流水线设计
传统的流水线设计是以转移指令为中心的，大量逻辑资源被用于提高处理器转移预测的能力，以保证向流水线发射和执行部件提供充足的指令流。在阵列众核处理器中提出了一种以访存为中心的核心流水线设计。通过提高访存装载指令在流水线中的执行优先级，以及访存装载指令的预测执行机制，可以有效减．少顺序流水线因访存延迟所带来的停顿，提高流水线性能和能效比。测试结果表明，以4KB容量的装载指令访存地址表为例，访存为中心的流水线设计可以带来8．6％的流水线性能提升和7％的流水线能效比提高。...
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| Published in | 计算机工程与科学 Vol. 39; no. 12; pp. 2167 - 2175 |
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| Main Author | |
| Format | Journal Article |
| Language | Chinese |
| Published |
数学工程与先进计算国家重点实验室,江苏无锡,214125
2017
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1007-130X |
| DOI | 10.3969/j.issn.1007-130X.2017.12.002 |
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| Summary: | 传统的流水线设计是以转移指令为中心的，大量逻辑资源被用于提高处理器转移预测的能力，以保证向流水线发射和执行部件提供充足的指令流。在阵列众核处理器中提出了一种以访存为中心的核心流水线设计。通过提高访存装载指令在流水线中的执行优先级，以及访存装载指令的预测执行机制，可以有效减．少顺序流水线因访存延迟所带来的停顿，提高流水线性能和能效比。测试结果表明，以4KB容量的装载指令访存地址表为例，访存为中心的流水线设计可以带来8．6％的流水线性能提升和7％的流水线能效比提高。 |
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| Bibliography: | ZHANG Kun, ZHENG Fang, XIE Xiang-hui （State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi 214125 ,China） Traditional processor pipeline is a branch-instruction-centric design where a large number of chip resources are used to improve the prediction accuracy of branches. We present a load-centric core pipeline design in array many-core processors. In the load-centric pipeline, the load instruction has high- er priority to be issued and executed. Besides, we also propose a prediction mechanism to generate the load instruction＇s source address in advance. The load-centric design decreases the stall latency of load instructionsand therefore improves the pipeline＇s performance and energy efficiency. Experimental results show that equipped with a 4KB size prediction table, the load-centric design can improve the pipe-line performance and energy efficiency by 8.6% and 7% respectively 43-1258/TP many-core processor; core pipeline; optimization of memory accesses; array many-coreprocessors |
| ISSN: | 1007-130X |
| DOI: | 10.3969/j.issn.1007-130X.2017.12.002 |