零级指令缓存研究综述

高效能是处理器设计的重要指标。由于指令部件在处理器芯片中开始占据越来越多的芯片面积,消耗了较多的芯片功耗,研究人员提出了零级指令缓存设计。零级指令缓存容量小、访问耗能低,与流水线紧密耦合、取指命中时可以门控流水线部分逻辑。因此,零级指令缓存可以有效提高流水线指令部件的能效比。综述了现有的零级指令缓存的不同结构、各结构的发展与应用情况;展望了零级指令缓存设计的未来研究思路。...

Full description

Saved in:
Bibliographic Details
Published in计算机工程与科学 Vol. 39; no. 3; pp. 405 - 412
Main Author 张昆 郝子宇 郑方 谢向辉
Format Journal Article
LanguageChinese
Published 数学工程与先进计算国家重点实验室,江苏无锡,214125 2017
Subjects
微体系结构设计
指令缓存
零级缓存
高效能
micro-architecture design
high energy-efficiency
L0 cache
instruction cache
指令缓存
零级缓存
微体系结构设计
高效能
Online AccessGet full text
ISSN1007-130X
DOI10.3969/j.issn.1007-130X.2017.03.001

Cover

More Information
Summary:高效能是处理器设计的重要指标。由于指令部件在处理器芯片中开始占据越来越多的芯片面积,消耗了较多的芯片功耗,研究人员提出了零级指令缓存设计。零级指令缓存容量小、访问耗能低,与流水线紧密耦合、取指命中时可以门控流水线部分逻辑。因此,零级指令缓存可以有效提高流水线指令部件的能效比。综述了现有的零级指令缓存的不同结构、各结构的发展与应用情况;展望了零级指令缓存设计的未来研究思路。
Bibliography:ZHANG Kun,HAO Zi-yu,ZHENG Fang,XIE Xiang-hui （State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi 214125,China）
43-1258/TP
high energy-efficiency; LO cache; instruction cache; micro-architecture design
Energy-efficiency becomes one of the key constraints in the current design of processors. Since the instruction unit accounts for considerable chip area and power consumption, we propose an L0 instruction cache （L0 IC） to alleviate the power cost of the instruction units. The L0 IC has small size so the access power is relatively small. Meanwhile the L0 IC is tightly coupled with the pipeline in order to clock-gate part of the pipeline logic when instruction fetches hit in the L0 IC. The recent studies on the L0 IC are reviewed. The development and application of each L0 IC design is presented. Meanwhile, fu ture work on the L0 IC design is discussed.
ISSN:1007-130X
DOI:10.3969/j.issn.1007-130X.2017.03.001