基于锁相环的高速示波器等效采样系统设计
采用小数分频锁相环芯片ADF4351作为采样时钟发生器,利用FPGA进行等精度测频,运用差频法顺序等效采样原理,设计了最高等效采样率为160 GS/s的高速示波器等效采样系统。同时通过时钟分配器和数字延迟线产生交替采样时钟,利用4片最高采样率为250 MS/s的8 bit ADC进行时间交替采样,使系统的最高实时采样率达到1 GS/s。由于采用低抖动的时钟源,系统在DC到500 MHz的设计带宽内保持了良好的噪声性能,信噪比优于基于DDS技术的等效采样系统。...
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Published in | 电子技术应用 Vol. 43; no. 5; pp. 94 - 97 |
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Main Author | |
Format | Journal Article |
Language | Chinese |
Published |
江苏省常熟中学,江苏苏州,215500%清华大学电机工程与应用电子技术系,北京,100084%南京邮电大学通信与信息工程学院,江苏南京,210023
2017
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Subjects | |
Online Access | Get full text |
ISSN | 0258-7998 |
DOI | 10.16157/j.issn.0258-7998.2017.05.023 |
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Summary: | 采用小数分频锁相环芯片ADF4351作为采样时钟发生器,利用FPGA进行等精度测频,运用差频法顺序等效采样原理,设计了最高等效采样率为160 GS/s的高速示波器等效采样系统。同时通过时钟分配器和数字延迟线产生交替采样时钟,利用4片最高采样率为250 MS/s的8 bit ADC进行时间交替采样,使系统的最高实时采样率达到1 GS/s。由于采用低抖动的时钟源,系统在DC到500 MHz的设计带宽内保持了良好的噪声性能,信噪比优于基于DDS技术的等效采样系统。 |
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Bibliography: | Using the fractional-N PLL chip ADF4351 as the sampling clock generator and FPGA for identical precision frequency measurement, an equivalent sampling system which has a maximum equivalent sampling rate of 160 GS/s is designed for high- speed oscilloscope under the beat frequency method sequential sampling principle. Combining the clock divider with the digital delay line to produce alternating sampling clock, and using four 8-bit ADC to finish time-interleaved sampling, this system's highest real-time sampling rate reached 1 GS/s. Due to the low jitter clock source, the system keeps low noise over the designed band- width of DC to 500 MHz, whose signal to noise ratio is better than that of the equivalent sampling system based on DDS. Zha Tianyi1, Chen Shengqi2, Ge Junyao3(1.Jiangsu Province Changshu High School, Suzhou 215500, China ; 2. Department of Electrical Engineering, Tsinghua University, Beijing 100084, China ; 3.College of Telecommunications & Information Engineering, Nangjing University of Posts and |
ISSN: | 0258-7998 |
DOI: | 10.16157/j.issn.0258-7998.2017.05.023 |