多通道雷达数字接收机数字下变频设计

提出一种基于时分复用原理的双频段多通道数字接收机DDC模块的设计方法,并利用FPGA的数控振荡器和FIR滤波器的IP核完成了DDC模块的设计与实现。仿真结果表明,该设计实现了数字混频、抽取和滤波的功能,与其他设计方案对比表明,本方案有效地减少了FPGA资源的使用量,降低了硬件设计的复杂度,节约了硬件成本。...

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Bibliographic Details
Published in电子技术应用 Vol. 42; no. 6; pp. 46 - 48
Main Author 黄世锋 陈章友 张兰 岳显昌
Format Journal Article
LanguageChinese
Published 武汉大学地球空间信息技术协同创新中心,湖北武汉430079 2016
武汉大学电子信息学院,湖北武汉,430072%武汉大学电子信息学院,湖北武汉430072
Subjects
同时双频段
多通道
数字下变频
数字接收机
时分复用
同时双频段
multi-channel
多通道
时分复用
time division multiplexing
数字下变频
digital receiver
two working bands synchronously
数字接收机
digital down-converter
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ISSN0258-7998
DOI10.16157/j.issn.0258-7998.2016.06.012

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Summary:提出一种基于时分复用原理的双频段多通道数字接收机DDC模块的设计方法,并利用FPGA的数控振荡器和FIR滤波器的IP核完成了DDC模块的设计与实现。仿真结果表明,该设计实现了数字混频、抽取和滤波的功能,与其他设计方案对比表明,本方案有效地减少了FPGA资源的使用量,降低了硬件设计的复杂度,节约了硬件成本。
Bibliography:A digital down- converter（DDC） module in a multi- channel digital radar receiver executed at two frequencies is designed based on time division multiplexing（TDM） technique, this new DDC designed by using intellectual ？ property（IP） cores of the numeri-cal controlled oscillator（NCO） and the finite impulse response（FIR） filter of a field programmable gate array（FPGA）. Simulation of this new designed DDC shows that these functions, such as digital mixer, decimation and filter have been achieved. Furthermore, this new DDC reduces the occupation of FPGA resources, simplifies the complexity of hardware design and reduces the cost of hardware.
Huang Shifeng,Chen Zhangyou ,Zhang Lan, Yue Xianchang （1.School of Electronics and Information, Wuhan University, Wuhan 430072, China; 2.Collaborative Innovation Center of Geospatial Technology,Wuhan 430079, China）
digital receiver; two working bands synchronously; multi-channel; digital down-converter; time division multiplexing
11-2305/TN
ISSN:0258-7998
DOI:10.16157/j.issn.0258-7998.2016.06.012