Two-stage logarithmic converter with reduced memory requirements

• Published in: Chronic diseases and translational medicine Vol. 8; no. 1; pp. 23 - 29
• Main Authors: Chaudhary, Mandeep, Lee, Peter
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.01.2014; Institution of Engineering and Technology; John Wiley & Sons, Inc
• Subjects: Accuracy; Algorithms; Applied sciences; Approximation; arithmetic components; binary logarithm; block RAM; Circuit properties; Clocks; Converters; convertors; Design. Technologies. Operation analysis. Testing; Devices; digital arithmetic; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Field programmable gate arrays; fractional precision; frequency 127.8 MHz; frequency 160 MHz; frequency 42.3 MHz; frequency 71.4 MHz; Integrated circuits; Integrated circuits by function (including memories and processors); Logic; logic slices; Mathematical models; Multipliers; nonuniform piecewise linear techniques; nonuniform piecewise polynomial techniques; normalised binary number conversion; Number systems; numeric precision; piecewise linear techniques; piecewise polynomial techniques; read‐only storage; reconfigurable architectures; reconflgurable fabric; reduced memory requirements; ROM; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing; Spartan6 XC6SLX16 device; storage capacity 11.3 Kbit; two‐stage logarithmic converter; uniform piecewise linear techniques; uniform piecewise polynomial techniques; Xilinx Spartan3 FPGA; Xilinx Spartan6 FPGA; piecewise polynomial techniques; arithmetic components; block RAM; field programmable gate arrays; numeric precision; reconflgurable fabric; reduced memory requirements; binary logarithm; convertors; reconfigurable architectures; digital arithmetic; logic slices; fractional precision; multipliers; normalised binary number conversion; nonuniform piecewise polynomial techniques; frequency 71.4 MHz; frequency 160 MHz; Xilinx Spartan3 FPGA; Spartan6 XC6SLX16 device; piecewise linear techniques; frequency 127.8 MHz; read-only storage; uniform piecewise polynomial techniques; Xilinx Spartan6 FPGA; nonuniform piecewise linear techniques; frequency 42.3 MHz; ROM; two-stage logarithmic converter; storage capacity 11.3 Kbit; uniform piecewise linear techniques; Performance evaluation; Arithmetic circuit; Read only memory(ROM); Multistage method; Random access memory; Field programmable gate array; Clock; Algorithm; Binary number; Implementation; Non volatile memory; Integrated circuit; Converter; Reconfigurable architectures; Piecewise linear system; Multiplying circuits; Multistage circuit; Piecewise linearization
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2012.0134

This study presents an efficient method for converting a normalised binary number x (1 ≤ x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.