Depletion-All-Around Operation of the SOI Four-Gate Transistor

• Published in: IEEE transactions on electron devices Vol. 54; no. 2; pp. 323 - 331
• Main Authors: Akarvardar, Kerem, Cristoloveanu, Sorin, Gentil, Pierre, Schrimpf, Ronald D., Blalock, Benjamin J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog; Analytical models; Applied sciences; Channels; Depletion; Devices; Early voltage; Electronics; Engineering Sciences; Exact sciences and technology; Gates; JFET; JFETs; Logic gates; low-frequency noise; Micro and nanotechnologies; Microelectronics; multiple-gate transistor; Oxides; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensitivity; Silicon; Silicon-on-insulator; silicon-on-insulator (SOI); Solid modeling; subthreshold swing; Three-dimensional displays; total-dose radiation-hardness; Transconductance; transconductance-to-current ratio; Transistors; Performance evaluation; subthreshold swing; Noise reduction; Junction field effect transistor; Transistor gate; JFET; Experimental device; 1/f noise; Modeling; Silicon on insulator technology; Radiation resistance; Ionizing radiation; Transconductance; Early voltage; Low noise circuit; transconductance-to-current ratio; Multiple gate transistor; total-dose radiation-hardness; Majority carrier; silicon-on-insulator (SOI); low-frequency noise; Radiation dose; Total radiation; Gate oxide; Analog; multiple-gate transistor
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.888749

In the silicon-on-insulator four-gate transistors (\hbox{G}^{4}\hbox{-}\hbox{FETs}) , the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The \hbox{G}^{4}\hbox{-}\hbox{FET} properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling.