A buffer minimization problem for the design of embedded systems

We consider a set of tasks, each of them is composed by a set of sequential operations, and a set of buffers. Each buffer b is defined between two tasks T i and T j , and is managed as a FIFO structure. Some operations from T i write data to the buffer b, others from T j get data from b. The writing...

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Bibliographic Details
Published inEuropean journal of operational research Vol. 164; no. 3; pp. 669 - 679
Main Authors Munier Kordon, Alix, Note, Jean-Baptiste
Format Journal Article Conference Proceeding
LanguageEnglish
Published Amsterdam Elsevier B.V 01.08.2005
Elsevier
Elsevier Sequoia S.A
SeriesEuropean Journal of Operational Research
Subjects
Online AccessGet full text
ISSN0377-2217
1872-6860
1872-6860
DOI10.1016/j.ejor.2004.01.041

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Summary:We consider a set of tasks, each of them is composed by a set of sequential operations, and a set of buffers. Each buffer b is defined between two tasks T i and T j , and is managed as a FIFO structure. Some operations from T i write data to the buffer b, others from T j get data from b. The writings and readings generate precedence constraints between the operations. The limitation of the size of the buffers generates another set of precedence constraints between them and circuits in the precedence graph may appear. In this case, there is no feasible schedule for the operations. The aim is to determine the size of each buffer such that the global surface of the buffers is minimized and there is no circuit in the precedence graph. We prove that this problem is polynomial for two tasks using a flow algorithm. We also prove that it is NP-complete in the strong sense for three tasks.
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ISSN:0377-2217
1872-6860
1872-6860
DOI:10.1016/j.ejor.2004.01.041