Customizable FPGA-Based Hardware Accelerator for Standard Convolution Processes Empowered with Quantization Applied to LiDAR Data

• Published in: Sensors (Basel, Switzerland) Vol. 22; no. 6; p. 2184
• Main Authors: Silva, João, Pereira, Pedro, Machado, Rui, Névoa, Rafael, Melo-Pinto, Pedro, Fernandes, Duarte
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 11.03.2022; MDPI
• Subjects: Algorithms; Classification; Computers; convolutional neural network (CNN); Deep learning; Energy consumption; field-programmable gate array (FPGA); hardware accelerator; light detection and ranging (LiDAR); Localization; Neural networks; object detection; Optimization; quantization; R&D; Research & development; Sensors; Software; Vehicles; light detection and ranging (LiDAR); object detection; convolutional neural network (CNN); field-programmable gate array (FPGA); hardware accelerator; quantization
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s22062184

In recent years there has been an increase in the number of research and developments in deep learning solutions for object detection applied to driverless vehicles. This application benefited from the growing trend felt in innovative perception solutions, such as LiDAR sensors. Currently, this is the preferred device to accomplish those tasks in autonomous vehicles. There is a broad variety of research works on models based on point clouds, standing out for being efficient and robust in their intended tasks, but they are also characterized by requiring point cloud processing times greater than the minimum required, given the risky nature of the application. This research work aims to provide a design and implementation of a hardware IP optimized for computing convolutions, rectified linear unit (ReLU), padding, and max pooling. This engine was designed to enable the configuration of features such as varying the size of the feature map, filter size, stride, number of inputs, number of filters, and the number of hardware resources required for a specific convolution. Performance results show that by resorting to parallelism and quantization approach, the proposed solution could reduce the amount of logical FPGA resources by 40 to 50%, enhancing the processing time by 50% while maintaining the deep learning operation accuracy.