Two-layer Bottleneck Channel Track Assignment for Analog VLSI

• Published in: IPSJ Transactions on System and LSI Design Methodology Vol. 17; pp. 67 - 76
• Main Authors: Minami, Makoto, Takahashi, Atsushi, Tayu, Satoshi, Molongo, Mathieu, Taniguchi, Kazuya, Nishioka, Katsuya
• Format: Journal Article
• Language: English
• Published: Tokyo Information Processing Society of Japan 01.01.2024; Japan Science and Technology Agency
• Subjects: Algorithms; Analog circuits; analog VLSI; bottleneck routing; channel routing; Integrated circuits
• ISSN: 1882-6687; 1882-6687
• DOI: 10.2197/ipsjtsldm.17.67

Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired. To reduce the layout area, “Bottleneck Channel Routing” is proposed in which two wires go through a routing track in the bottleneck region. A two-layer routing problem that consists of the bottleneck channel and the adjacent regions where the HV rule is not applicable is defined. The proposed algorithm uses a U-shaped routing model, and generates two-layer routing in which the number of intersections is minimized and the wire of a net includes at most one via. The obtained routing contains no conflicts if the algorithm outputs a feasible solution.