Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm

• Published in: IEEE transactions on parallel and distributed systems Vol. 22; no. 7; pp. 1142 - 1149
• Main Authors: Ibrahim, A, Gebali, F, Elsimary, H, Nassar, A
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Architecture; Arrays; cryptography; Equations; Hardware; Indexes; low power modular multipliers; Methodology; Modular; Montgomery multiplication; Multiplication; Power consumption; Power demand; Processor array; Processor arrays; scalability; secure communications; Switching; Timing
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2010.196

This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.