Design of a BIST implemented AES crypto-processor ASIC

• Published in: PloS one Vol. 16; no. 11; p. e0259956
• Main Authors: Ali, Md. Liakot, Rahman, Md. Shazzatur, Hossain, Fakir Sharif
• Format: Journal Article
• Language: English
• Published: United States Public Library of Science 16.11.2021; Public Library of Science (PLoS)
• Subjects: Acidity; Algorithms; Analysis; Application specific integrated circuits; Automation; Communication; Computer and Information Sciences; Computer Security - instrumentation; Computer Simulation; Cryptography; Design; Design and construction; Electronic design automation; Engineering and Technology; Evaluation; Field programmable gate arrays; Hardware description languages; High density lipoprotein; Industry; Industry standards; Information technology; Integrated circuits; Microprocessors; Optimization; Pattern Recognition, Automated; Physical Sciences; Pseudorandom; Research and Analysis Methods; Research design; Security; Self tests; Semiconductor chips; Social Sciences; Sodium channels; Software; Testability; United States; United States; Bangladesh; United States > US
• ISSN: 1932-6203; 1932-6203
• DOI: 10.1371/journal.pone.0259956

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.