Design and Implementation of Opto-Electrical Hybrid Floating-Point Multipliers

• Published in: IEICE Transactions on Information and Systems Vol. E108.D; no. 1; pp. 2 - 11
• Main Authors: INOUE, Koji, KAWAKAMI, Satoshi, ONO, Takatsugu, INABA, Takumi
• Format: Journal Article
• Language: English
• Published: Tokyo The Institute of Electronics, Information and Communication Engineers 01.01.2025; Japan Science and Technology Agency
• Subjects: Accuracy; analog computing; Circuits; Energy consumption; Floating point arithmetic; floating-point multiplier; Multipliers; opto-electrical circuit; silicon photonics
• ISSN: 0916-8532; 1745-1361; 1745-1361
• DOI: 10.1587/transinf.2024PAP0003

The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate for tackling the issue due to its ultra-low latency, high bandwidth, and low power characteristics. Although previous research develops hardware accelerators by exploiting nanophotonic circuits for AI inference applications, there has never been considered for the acceleration of training that requires complex Floating-Point (FP) operations. In particular, the design balance between optical and electrical circuits has a critical impact on the latency, energy, and accuracy of the arithmetic system, and thus requires careful consideration of the optimal design. In this study, we design three types of Opto-Electrical Floating-point Multipliers (OEFMs): accuracy-oriented (Ao-OEFM), latency-oriented (Lo-OEFM), and energy-oriented (Eo-OEFM). Based on our evaluation, we confirm that Ao-OEFM has high noise resistance, and Lo-OEFM and Eo-OEFM still have sufficient calculation accuracy. Compared to conventional electrical circuits, Lo-OEFM achieves an 87% reduction in latency, and Eo-OEFM reduces energy consumption by 42%.