High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion

• Published in: Chronic diseases and translational medicine Vol. 9; no. 3; pp. 175 - 184
• Main Authors: Liu, Qiang, Xu, Zhenyu, Yuan, Ye
• Format: Journal Article
• Language: English
• Published: Beijing The Institution of Engineering and Technology 01.05.2015; John Wiley & Sons, Inc
• Subjects: AES design; bit rate 100 Gbit/s; bit rate 75.9 Gbit/s; Critical path; cryptography; Data encryption; data protection; Demand; Design analysis; Design standards; Devices; Encryption; enhanced key expansion scheme; field programmable gate array; Field programmable gate arrays; FPGA architectures; high speed data protection; high throughput advanced encryption standard; image encryption; Logic; logic design; nonlinear operations; N‐round AES; Pipelining (computers); pipelining structures; power consumption; real‐time encryption‐decryption demand; secure advanced encryption standard; Storage area networks; Zynq xc7z020 FPGA platform; bit rate 75.9 Gbit/s; field programmable gate arrays; AES design; pipelining structures; real-time encryption-decryption demand; Zynq xc7z020 FPGA platform; high throughput advanced encryption standard; cryptography; bit rate 100 Gbit/s; nonlinear operations; N-round AES; image encryption; power consumption; field programmable gate array; high speed data protection; data protection; FPGA architectures; secure advanced encryption standard; enhanced key expansion scheme; logic design
• ISSN: 1751-8601; 1751-861X; 2095-882X; 1751-861X; 2589-0514
• DOI: 10.1049/iet-cdt.2014.0101

Aiming at protection of high speed data, field programmable gate array (FPGA)-based advanced encryption standard (AES) design is proposed here. Deep investigation into the logical operations of AES with regard to FPGA architectures leads to two efficient pipelining structures for the AES hardware implementation. The two design options allow users to make a trade-off among speed, resource usage and power consumption. In addition, a new key expansion scheme is proposed to address the potential issues of existing key expansion scheme used in AES. The proposed key expansion scheme with additional non-linear operations increases the complexity of cracking keys by up to 2(N − 1) times for N-round AES. The proposed design is evaluated on various FPGA devices and is compared with several existing AES implementations. In terms of both throughput and throughput per slice, the proposed design can overcome most existing designs and achieves a throughput of 75.9 Gbps on a latest FPGA device. Two parallel implementations of the proposed design can meet the real-time encryption/decryption demand for 100 Gbps data rate. Furthermore, the proposed AES design is implemented on the Zynq xc7z020 FPGA platform, demonstrating its application to image encryption.