A Real-Time FPGA-Based Metaheuristic Processor to Efficiently Simulate a New Variant of the PSO Algorithm

• Published in: Micromachines (Basel) Vol. 14; no. 4; p. 809
• Main Authors: Anides, Esteban, Salinas, Guillermo, Pichardo, Eduardo, Avalos, Juan G., Sánchez, Giovanny, Sánchez, Juan C., Sánchez, Gabriel, Vazquez, Eduardo, Toscano, Linda K.
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 31.03.2023; MDPI
• Subjects: Acoustic cancellers; Acoustics; AEC system; Algorithms; Digital integrated circuits; Field programmable gate arrays; FPGA; Heuristic methods; Markov analysis; Markovian switching technique; Mathematical optimization; Microprocessors; parallel metaheuristic processor; Particle swarm optimization; spiking neural P systems; Time multiplexing; Mexico; parallel metaheuristic processor; AEC system; spiking neural P systems; particle swarm optimization; Markovian switching technique; FPGA
• ISSN: 2072-666X; 2072-666X
• DOI: 10.3390/mi14040809

Nowadays, high-performance audio communication devices demand superior audio quality. To improve the audio quality, several authors have developed acoustic echo cancellers based on particle swarm optimization algorithms (PSO). However, its performance is reduced significantly since the PSO algorithm suffers from premature convergence. To overcome this issue, we propose a new variant of the PSO algorithm based on the Markovian switching technique. Furthermore, the proposed algorithm has a mechanism to dynamically adjust the population size over the filtering process. In this way, the proposed algorithm exhibits great performance by reducing its computational cost significantly. To adequately implement the proposed algorithm in a Stratix IV GX EP4SGX530 FPGA, we present for the first time, the development of a parallel metaheuristic processor, in which each processing core simulates the different number of particles by using the time-multiplexing technique. In this way, the variation of the size of the population can be effective. Therefore, the properties of the proposed algorithm along with the proposed parallel hardware architecture potentially allow the development of high-performance acoustic echo canceller (AEC) systems.