Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms

A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good...

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Published inSensors (Basel, Switzerland) Vol. 24; no. 2; p. 409
Main Authors Grenier, Antoine, Lei, Jie, Damsgaard, Hans Jakob, Quintana-Ortí, Enrique S., Ometov, Aleksandr, Lohan, Elena Simona, Nurmi, Jari
Format Journal Article
LanguageEnglish
Published Switzerland MDPI AG 01.01.2024
MDPI
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ISSN1424-8220
1424-8220
DOI10.3390/s24020409

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Abstract A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.
AbstractList A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.
A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as Application-Specific Integrated Circuit (ASIC)s off-the-shelf, each tailored to the requirements of various applications. These chips deliver good performance and low energy consumption but offer customers little-to-no transparency about their internal features. This prevents modification, research in GNSS processing chain enhancement (e.g., application of Approximate Computing (AxC) techniques), and design space exploration to find the optimal receiver for a use case. In this paper, we review the GNSS processing chain using SyDR, our open-source GNSS Software-Defined Radio (SDR) designed for algorithm benchmarking, and highlight the limitations of a software-only environment. In return, we propose an evolution to our system, called Hard SyDR to become closer to the hardware layer and access new Key Performance Indicator (KPI)s, such as power/energy consumption and resource utilization. We use High-Level Synthesis (HLS) and the PYNQ platform to ease our development process and provide an overview of their advantages/limitations in our project. Finally, we evaluate the foreseen developments, including how this work can serve as the foundation for an exploration of AxC techniques in future low-power GNSS receivers.
Audience Academic
Author Lei, Jie
Ometov, Aleksandr
Damsgaard, Hans Jakob
Lohan, Elena Simona
Quintana-Ortí, Enrique S.
Nurmi, Jari
Grenier, Antoine
AuthorAffiliation 2 Parallel Architectures Group, Universitat Politècnica de València, 46010 Valencia, Spain; jlei@disca.upv.es (J.L.); quintana@disca.upv.es (E.S.Q.-O.)
1 Electrical Engineering Unit, Tampere University, 33720 Tampere, Finland; hans.damsgaard@tuni.fi (H.J.D.); aleksandr.ometov@tuni.fi (A.O.); elena-simona.lohan@tuni.fi (E.S.L.); jari.nurmi@tuni.fi (J.N.)
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– name: 2 Parallel Architectures Group, Universitat Politècnica de València, 46010 Valencia, Spain; jlei@disca.upv.es (J.L.); quintana@disca.upv.es (E.S.Q.-O.)
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Keywords open-source software
global navigation satellite system (GNSS)
benchmarking
field-programmable gate array (FPGA)
computational complexity
Language English
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These authors contributed equally to this work.
This paper is an extended version of our paper published in ICL-GNSS 2023, Castellon, Spain, 6–8 June 2023.
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Snippet A Global Navigation Satellite System (GNSS) is widely used today for both positioning and timing purposes. Many distinct receiver chips are available as...
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StartPage 409
SubjectTerms Algorithms
Application-specific integrated circuits
Approximation
Artificial satellites
benchmarking
Benchmarks
Communications equipment
computational complexity
Custom integrated circuits
Design
Discovery and exploration
Energy consumption
Field programmable gate arrays
field-programmable gate array (FPGA)
Fourier transforms
global navigation satellite system (GNSS)
open-source software
Outer space
Public software
Python
Radios
Receivers & amplifiers
Satellites
Semiconductor industry
Software
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Title Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms
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