New Systolic Array Algorithms and VLSI Architectures for 1-D MDST

In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regu...

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Published inSensors (Basel, Switzerland) Vol. 23; no. 13; p. 6220
Main Authors Chiper, Doru Florin, Cracan, Arcadie
Format Journal Article
LanguageEnglish
Published Switzerland MDPI AG 07.07.2023
MDPI
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ISSN1424-8220
1424-8220
DOI10.3390/s23136220

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Summary:In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regular computational structures called pseudo-circular correlation and pseudo-cycle convolution. The two computational structures for pseudo-circular correlation and pseudo-cycle convolution both have the same form. This feature can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array. Moreover, the second algorithm can be used to further reduce the hardware complexity by replacing the general multipliers from the first one with multipliers with a constant that have a significantly reduced complexity. The resulting VLSI architectures have all the advantages of a cycle convolution and circular correlation based systolic implementations, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology, and low I/O cost. Moreover, in both architectures, a cost-effective application of an obfuscation technique can be achieved with low overheads.
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This paper is an extension of our conference paper presented at the International Symposium on Electronics and Telecommunications ISETC 2022. Chiper, D.F.; Cracan, A. A New VLSI Algorithm for a VLSI Implementation of MDST using Obfuscation Technique. In Proceedings of the 2022 International Symposium on Electronics and Telecommunications (ISETC), Timisoara, Romania, 10–11 November 2022; pp. 1–4.
ISSN:1424-8220
1424-8220
DOI:10.3390/s23136220