Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

• Published in: Sensors (Basel, Switzerland) Vol. 22; no. 7; p. 2570
• Main Author: Lai, Wen-Cheng
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 27.03.2022; MDPI
• Subjects: all-digital; Circuits; Communication; frequency synthesizer; Frequency synthesizers; Noise; reference spur reduction; Sensors; reference spur reduction; all-digital; frequency synthesizer
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s22072570

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.