Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 50; no. 8; pp. 1764 - 1771
• Main Authors: Kinyua, Martin, Ruopeng Wang, Soenen, Eric
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Audio power amplifier; Batteries; Capacitors; class-D amplifier; CMOS; Control systems; Control theory; Design engineering; Digital; Gain; Noise; Noise levels; power supply rejection ratio (PSRR); Product design; Pulse duration modulation; Pulse width modulation; pulse-width modulation (PWM); Switches; total harmonic distortion and noise ({\rm THD}+{\rm N}); Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2015.2420314

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 Ω speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.