A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array

• Published in: IEEE transactions on circuits and systems for video technology Vol. 11; no. 11; pp. 1149 - 1159
• Main Authors: HSIAO, Shen-Fu, SHIUE, Wei-Ren
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2001; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Architecture; Arithmetic; Computation; Computer architecture; Costs; Discrete cosine transforms; Exact sciences and technology; Fast Fourier transforms; Hardware; Information, signal and communications theory; Mathematical analysis; Mathematical methods; Matrices; Matrix converters; Matrix decomposition; Multipliers; Neural networks; Partitioning algorithms; Recursive; Telecommunications and information theory; Vectors; Circuit architecture; Arithmetic circuit; VLSI circuit; Linear array; Signal processing; Image compression; Systolic network; Discrete cosine transforms; Recursive algorithm
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/76.964780

A new recursive algorithm with hardware complexity of O(log/sub 2/N) is derived for fast computation of N/spl times/N 2-D discrete cosine transforms (2-D DCTs). It first converts the original 2-D data matrices into 1-D vectors and then employs different partition methods for the input and output indices in the 1-D vector space. Afterward, the algorithm computes the corresponding 2-D complex DCT (2-D CCT) and then uses a post-addition step to produce simultaneously two 2-D DCT outputs. The decomposed form of the 2-D recursive algorithm looks like a radix-4 fast Fourier transform algorithm. The common entries in each row of the butterfly-like matrix are factored out in order to reduce the number of multipliers needed during implementation. A new linear architecture for the derived algorithm is presented which leads to a hardware-efficient architectural design requiring only log/sub 2/N complex multipliers plus 3log/sub 2/N complex adders/subtractors for the computation of a 2-D N/spl times/N CCT.