Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces

• Published in: Sensors (Basel, Switzerland) Vol. 24; no. 3; p. 899
• Main Authors: Martín-Martín, Alberto, Padial-Allué, Rubén, Castillo, Encarnación, Parrilla, Luis, Parellada-Serrano, Ignacio, Morán, Alejandro, García, Antonio
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 30.01.2024
• Subjects: Algorithms; Artificial intelligence; Comparative analysis; Data processing; Deep learning; Digital integrated circuits; Edge computing; Field programmable gate arrays; Forecasts and trends; FPGA; Internet of Things; Neural networks; Optimization; R&D; Receivers & amplifiers; reconfigurable intelligent surfaces; Research & development; Semiconductor industry; Telecommunication systems; Wireless communications; Iran; United States; reconfigurable intelligent surfaces; 6G; FPGA; artificial intelligence; neural networks
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s24030899

Reconfigurable intelligent surfaces (RIS) offer the potential to customize the radio propagation environment for wireless networks, and will be a key element for 6G communications. However, due to the unique constraints in these systems, the optimization problems associated to RIS configuration are challenging to solve. This paper illustrates a new approach to the RIS configuration problem, based on the use of artificial intelligence (AI) and deep learning (DL) algorithms. Concretely, a custom convolutional neural network (CNN) intended for edge computing is presented, and implementations on different representative edge devices are compared, including the use of commercial AI-oriented devices and a field-programmable gate array (FPGA) platform. This FPGA option provides the best performance, with ×20 performance increase over the closest FP32, GPU-accelerated option, and almost ×3 performance advantage when compared with the INT8-quantized, TPU-accelerated implementation. More noticeably, this is achieved even when high-level synthesis (HLS) tools are used and no custom accelerators are developed. At the same time, the inherent reconfigurability of FPGAs opens a new field for their use as enabler hardware in RIS applications.