Carbon-nanotube-based voltage-mode multiple-valued logic design

• Published in: IEEE transactions on nanotechnology Vol. 4; no. 2; pp. 168 - 179
• Main Authors: Raychowdhury, A., Roy, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Carbon; Carbon nanotubes; Circuit properties; CMOS; CMOS logic circuits; CMOS process; CNTFETs; Design; Design engineering; Digital circuits; Digital systems; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Electronics industry; Exact sciences and technology; Geometry; Logic; Logic design; Molecular electronics, nanoelectronics; Multivalued logic; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solid modeling; Threshold voltage; Transistors; Performance evaluation; Voltage threshold; Voltage dependence; Nanotube devices; Transfer characteristic; Carbon nanotubes; Multivalued logic; Logic gate; Logic design; Ballistic transport; Implementation; Nanoelectronics; Logic circuit; Field effect transistor; SPICE; Voltage mode; Comparative study
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2004.842068

Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a/spl grave/-vis traditional complementary field-effect transistor binary logic family has been presented.