New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications

• Published in: IEEE transactions on consumer electronics Vol. 49; no. 1; pp. 14 - 20
• Main Authors: Jung, Yunho, Yoon, Hongil, Kim, Jaeseok
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; CMOS; CMOS logic circuits; CMOS process; CMOS technology; Counting; Electronics; Hardware; Logic gates; Logic synthesis; Microprocessors; Multimedia communication; Multimedia systems; OFDM modulation; Orthogonal Frequency Division Multiplexing; Pipelines; Studies; Wireless communication; Wireless LAN
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2003.1205450

In this paper, we propose a new efficient FFT algorithm for OFDM/DMT applications and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-23 algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-2/sup 3/ algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.35 /spl mu/m CMOS technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the OFDM/DMT applications such as the WLAN, DAB/DVB, and ADSL/VDSL systems.