A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are...

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Published inIEEE access Vol. 8; p. 1
Main Authors Podobas, Artur, Sano, Kentaro, Matsuoka, Satoshi
Format Journal Article
LanguageEnglish
Published Piscataway IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN2169-3536
2169-3536
DOI10.1109/ACCESS.2020.3012084

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Abstract With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.
AbstractList With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.
Author Podobas, Artur
Matsuoka, Satoshi
Sano, Kentaro
Author_xml – sequence: 1
  givenname: Artur
  surname: Podobas
  fullname: Podobas, Artur
  organization: RIKEN Center for Computational Science, Kobe, Hyogo, Japan and KTH Royal Institute of Technology, Stockholm, Sweden. (e-mail: artur@podobas.net)
– sequence: 2
  givenname: Kentaro
  surname: Sano
  fullname: Sano, Kentaro
  organization: RIKEN Center for Computational Science, Kobe, Hyogo, Japan
– sequence: 3
  givenname: Satoshi
  surname: Matsuoka
  fullname: Matsuoka, Satoshi
  organization: RIKEN Center for Computational Science, Kobe, Hyogo, Japan and Tokyo Institute of Technology, Tokyo, Japan
BackLink https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281172$$DView record from Swedish Publication Index
BookMark eNp9kU9v1DAQxSNUJErpJ-glEucsHv9LfIxCKZUqUbHQq-U4k9bLbrzYTqt-e7xNqYADvng0fu83tt_b4mjyExbFGZAVAFEf2q47X69XlFCyYgQoafir4piCVBUTTB79Ub8pTmPckLya3BL1cXHTlus53ONj6aey8yZErC6CcRMO5Ve0fhrd7RxMv8WyDfbOJbRpDhjLMfhdacprDKMPOzNZPNRxn8_dPb4rXo9mG_H0eT8pvn86_9Z9rq6-XFx27VVlOZepYtQoUhusoRYwCGiaoZfMkkYaLgahBKMCrZH9oCSVIDkdBWdqqCmgtaphJ8Xlwh282eh9cDsTHrU3Tj81fLjVJiRnt6h7OvImT4WR1nzItUEwYIaMGkGCyqxqYcUH3M_9X7SP7qZ9ov1Id5o2ADXN-veLfh_8zxlj0hs_hyk_V1MuuOSMkQNVLSobfIwBR21dMsn5KeVv3mog-pCiXlLUhxT1c4rZy_7x_r7T_11ni8sh4otDAVeSAPsF3pipGA
CODEN IAECCG
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ContentType Journal Article
Copyright Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020
Copyright_xml – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020
DBID 97E
ESBDL
RIA
RIE
AAYXX
CITATION
7SC
7SP
7SR
8BQ
8FD
JG9
JQ2
L7M
L~C
L~D
ADTPV
AFDQA
AOWAS
D8T
D8V
ZZAVC
DOA
DOI 10.1109/ACCESS.2020.3012084
DatabaseName IEEE All-Society Periodicals Package (ASPP) 2005–Present
IEEE Xplore Open Access Journals
IEEE All-Society Periodicals Package (ASPP) 1998–Present
IEEE/IET Electronic Library (IEL) (UW System Shared)
CrossRef
Computer and Information Systems Abstracts
Electronics & Communications Abstracts
Engineered Materials Abstracts
METADEX
Technology Research Database
Materials Research Database
ProQuest Computer Science Collection
Advanced Technologies Database with Aerospace
Computer and Information Systems Abstracts – Academic
Computer and Information Systems Abstracts Professional
SwePub
SWEPUB Kungliga Tekniska Högskolan full text
SwePub Articles
SWEPUB Freely available online
SWEPUB Kungliga Tekniska Högskolan
SwePub Articles full text
DOAJ Directory of Open Access Journals
DatabaseTitle CrossRef
Materials Research Database
Engineered Materials Abstracts
Technology Research Database
Computer and Information Systems Abstracts – Academic
Electronics & Communications Abstracts
ProQuest Computer Science Collection
Computer and Information Systems Abstracts
Advanced Technologies Database with Aerospace
METADEX
Computer and Information Systems Abstracts Professional
DatabaseTitleList


Materials Research Database
Database_xml – sequence: 1
  dbid: DOA
  name: DOAJ Open Access Full Text
  url: https://www.doaj.org/
  sourceTypes: Open Website
– sequence: 2
  dbid: RIE
  name: IEEE Xplore
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISSN 2169-3536
EndPage 1
ExternalDocumentID oai_doaj_org_article_b2f484461f274df48ae1a1ad21ef1619
oai_DiVA_org_kth_281172
10_1109_ACCESS_2020_3012084
9149601
Genre orig-research
GrantInformation_xml – fundername: New Energy and Industrial Technology Development Organization
  funderid: 10.13039/501100001863
GroupedDBID 0R~
5VS
6IK
97E
AAJGR
ABAZT
ABVLG
ACGFS
ADBBV
ALMA_UNASSIGNED_HOLDINGS
BCNDV
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
EBS
ESBDL
GROUPED_DOAJ
IPLJI
JAVBF
KQ8
M43
M~E
O9-
OCL
OK1
RIA
RIE
RNS
4.4
AAYXX
AGSQL
CITATION
EJD
RIG
7SC
7SP
7SR
8BQ
8FD
JG9
JQ2
L7M
L~C
L~D
ADTPV
AFDQA
AOWAS
D8T
D8V
ZZAVC
ID FETCH-LOGICAL-c446t-32a907ae71751d5188db63c086a45d595325eca6bd96261642f5439d721ecc983
IEDL.DBID RIE
ISSN 2169-3536
IngestDate Wed Aug 27 01:22:08 EDT 2025
Thu Aug 21 06:45:49 EDT 2025
Mon Jun 30 06:17:59 EDT 2025
Tue Jul 01 02:55:39 EDT 2025
Thu Apr 24 23:05:34 EDT 2025
Wed Aug 27 02:33:35 EDT 2025
IsDoiOpenAccess true
IsOpenAccess true
IsPeerReviewed true
IsScholarly true
Language English
License https://creativecommons.org/licenses/by/4.0/legalcode
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-c446t-32a907ae71751d5188db63c086a45d595325eca6bd96261642f5439d721ecc983
Notes ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ORCID 0000-0001-5452-6794
OpenAccessLink https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/document/9149601
PQID 2454643309
PQPubID 4845423
PageCount 1
ParticipantIDs proquest_journals_2454643309
ieee_primary_9149601
crossref_primary_10_1109_ACCESS_2020_3012084
doaj_primary_oai_doaj_org_article_b2f484461f274df48ae1a1ad21ef1619
crossref_citationtrail_10_1109_ACCESS_2020_3012084
swepub_primary_oai_DiVA_org_kth_281172
ProviderPackageCode CITATION
AAYXX
PublicationCentury 2000
PublicationDate 2020-01-01
PublicationDateYYYYMMDD 2020-01-01
PublicationDate_xml – month: 01
  year: 2020
  text: 2020-01-01
  day: 01
PublicationDecade 2020
PublicationPlace Piscataway
PublicationPlace_xml – name: Piscataway
PublicationTitle IEEE access
PublicationTitleAbbrev Access
PublicationYear 2020
Publisher IEEE
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml – name: IEEE
– name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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SSID ssj0000816957
Score 2.4946985
Snippet With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to...
With the end of both Dennard’s scaling and Moore’s law, computer users and researchers are aggressively exploring alternative forms of computing in order to...
SourceID doaj
swepub
proquest
crossref
ieee
SourceType Open Website
Open Access Repository
Aggregation Database
Enrichment Source
Index Database
Publisher
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SubjectTerms CGRA
Clocks
Coarse-Grained Reconfigurable Architectures
Computation
Computing Trends
Field programmable gate arrays
FPGA
High-Performance Computing
Parallel programming
Post-Moore
Random access memory
Reconfigurable control systems
Reconfigurable systems
Silicon
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SummonAdditionalLinks – databaseName: DOAJ Directory of Open Access Journals
  dbid: DOA
  link: http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwrZ3PT4MwFMcb40kPxp9x_koPxpNktFBGjzidxkRjolt2a0pb1KhgJjPxv_c9YJNd9OKNEErpe6W8D_C-j5BjX6dxL3WpF5sswpSczAOyNR5nJspCXBAjzEa-uY2uhuH1WIxbpb7wn7BaHrg2XDflWRgDs7AM-MnCtnZMM205cxlEK1Xqni_9FkxVa3DMIil6jcwQ82U36fdhRACEHDgVM0bjcOFRVCn2NyVWFqPNtoJo9dQZrJO1JlykSX2ZG2TJ5ZtktSUiuEVGCb2fTj7dFy1y2i8AVJ13iYUfnKUIl3n2_DidYIYUTVpfDT7oYFK8UU3vflIHcHuWerlNhoOLh_6V11RL8AyYp_QCrgF0tQM-E8yizppNo8AAsuhQWCFFwIUzOkqtBIgBSuKZgGjEAgKCG2Uc7JDlvMjdLqEh6xnAwpQ7w0Pha23B-qbHWGQls8zvED4znDKNlDhWtHhVFVL4UtXWVmht1Vi7Q07njd5rJY3fDz9Dj8wPRRnsagdMDtVMDvXX5OiQLfTn_CQSeBAItEMOZv5VzS37oWCkIYRngQ-tTmqfL3R-_jxKqs5fyifFMT-X7_3HNe6TFRx3_VrngCyXk6k7hECnTI-qOf0Nsln17w
  priority: 102
  providerName: Directory of Open Access Journals
Title A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective
URI https://ieeexplore.ieee.org/document/9149601
https://www.proquest.com/docview/2454643309
https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281172
https://doaj.org/article/b2f484461f274df48ae1a1ad21ef1619
Volume 8
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1Nb9QwELVKT3DgqyAW2soHxKnZxo6dxMewpVRIRUjQqjfLX4GqKIu2CRL8emYcb9hFCHGzIif2aCbxPDvvDSEvc2Prygab1a4tkZLTZoBsXcaZK1uBH8QS2cjn78uzC_HuSl7tkKOJCxNCiD-fhTk241m-X7oBt8qOFaTzJZK17kCYjVytaT8FC0goWSVhIZar42axABsAAnJApsgRrcXW4hM1-lNRle38clMzNK4zpw_I-XqG4-8lN_Oht3P38w_xxv814SG5nxJO2owR8ojshO4xubchQ7hHLhv6cVh9Dz_osqOLJUDdkL3F0hHBU4SnXXv9eVghx4o2G-cOtxS5KdTQD7_JB9hekzefkIvTN58WZ1mqt5A5AIV9VnADUNkEQHiSeVRq87YsHIAeI6SXShZcBmdK6xXAIMBZvJWQz3gAkRAIqi6ekt1u2YVnhApWOQCWlgfHhcyN8azlrmKs9Ip5ls8IXztCuyRGjjUxvuoISnKlR-9p9J5O3puRo-mmb6MWx7-7v0YPT11RSDteAIfo9F5qy1tRg_UwvUp4aJvADDMeTGohGVYzsodOnB6S_Dcj--t40emlv9VgqYAEr8jhrldjDG0NfnJ92cTBb_ovmiPDlz__--NfkLtoybjVs092-9UQDiD56e1h3DQ4jLH_C0zEAII
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1Nb9QwELWqcgAOFCio2xbwAXFqtrFjJ_ExLJQFuhUSbdWb5a9AVZSttglS--uZSbJhFyHEzYr8NRo7nufkvSHkdWxsntlgo9yVKVJyygiQrYs4c2kp8IWYIht5dpJOz8SnC3mxQQ4GLkwIof35LIyx2H7L93PX4FXZoYJwPkWy1j0JqCLv2FrDjQqmkFAy66WFWKwOi8kErAAQyAGbIks0F2vHT6vS36dVWY8wV1VD25PmaIvMlnPsfjC5Gje1Hbu7P-Qb_9eIx-RRH3LSolsjT8hGqJ6ShytChNvkvKBfm8XPcEvnFZ3MAeyG6AMmjwieIkCtystvzQJZVrRY-fJwQ5GdQg398pt-gOUlffMZOTt6fzqZRn3GhcgBLKyjhBsAyyYAxpPMo1abt2niAPYYIb1UMuEyOJNarwAIAdLipYSIxgOMhKWg8uQ52azmVdghVLDMAbS0PDguZGyMZyV3GWOpV8yzeET40hHa9XLkmBXjh25hSax05z2N3tO990bkYGh03alx_Lv6W_TwUBWltNsH4BDd70xteSlysB6mlwkPZROYYcaDSSWEw2pEttGJQye9_0Zkf7ledL_tbzRYKiDES2Jo9aZbQ2uDv7s8L9rBr-rvmiPHl-_-vftX5P70dHasjz-efN4jD9Cq7uJnn2zWiya8gFCoti_bHfAL4WsC4A
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+Survey+on+Coarse-Grained+Reconfigurable+Architectures+From+a+Performance+Perspective&rft.jtitle=IEEE+access&rft.au=Podobas%2C+Artur&rft.au=Sano%2C+Kentaro&rft.au=Matsuoka%2C+Satoshi&rft.date=2020-01-01&rft.issn=2169-3536&rft.eissn=2169-3536&rft.volume=8&rft.spage=146719&rft.epage=146743&rft_id=info:doi/10.1109%2FACCESS.2020.3012084&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_ACCESS_2020_3012084
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2169-3536&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2169-3536&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2169-3536&client=summon