A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

• Published in: IEEE access Vol. 8; p. 1
• Main Authors: Podobas, Artur, Sano, Kentaro, Matsuoka, Satoshi
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CGRA; Clocks; Coarse-Grained Reconfigurable Architectures; Computation; Computing Trends; Field programmable gate arrays; FPGA; High-Performance Computing; Parallel programming; Post-Moore; Random access memory; Reconfigurable control systems; Reconfigurable systems; Silicon; Table lookup
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2020.3012084

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of CGRAs. We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.