A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

• Published in: IPSJ Transactions on System LSI Design Methodology Vol. 7; pp. 81 - 90
• Main Authors: Hagio, Yuta, Yanagisawa, Masao, Togawa, Nozomu
• Format: Journal Article
• Language: English
• Published: Tokyo Information Processing Society of Japan 2014; Japan Science and Technology Agency
• Subjects: Algorithms; Binding; Delay; distributed-register architecture; High level synthesis; Level (quantity); post-silicon tuning; process and delay variation; Scheduling
• ISSN: 1882-6687; 1882-6687
• DOI: 10.2197/ipsjtsldm.7.81

As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection delays even in high-level synthesis. Using RDR architectures is one of the effective solutions to this problem. At the same time, process and delay variation also becomes a serious problem which may result in several timing errors. How to deal with this problem is another key issue in high-level synthesis. In this paper, we propose a delay-variation-aware high-level synthesis algorithm for RDR architectures. We first obtain a non-delayed scheduling/binding result and, based on it, we also obtain a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we can have a delayed scheduling/binding result so that its latency is not much increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.