A new design approach of hardware implementation through natural language entry

• Published in: IET collaborative intelligent manufacturing Vol. 5; no. 4
• Main Authors: Yang, Kaiyuan, Liu, Haotian, Zhao, Yuqin, Deng, Tiantai
• Format: Journal Article
• Language: English
• Published: Wuhan John Wiley & Sons, Inc 01.12.2023; Wiley
• Subjects: Accelerators; Algorithms; Artificial intelligence; Automation; Case studies; Chatbots; computer integrated manufacturing; Design; Designers; Field programmable gate arrays; Generative artificial intelligence; Hardware; human computer interaction; human‐robot interaction; Intellectual property; intelligent manufacturing systems; Language; Natural language; Natural language processing; Workflow
• ISSN: 2516-8398; 2516-8398
• DOI: 10.1049/cim2.12087

OpenAI's ChatGPT (GPT‐4) ushers in a superior mode of computer interaction through natural language dialogues. Notably, it generates not only engaging dialogues but also codes aligned to queries and requirements. The potential of ChatGPT in hardware implementation via natural language is implemented and a strategy for “asking the right questions” is outlined. The versatility of ChatGPT is demonstrated through three mainstream hardware designs – systolic array, ResNet and MobileNet accelerators – comparing these with hand‐coded designs. The evaluation metrics include design quality, design efforts, and limitations of code generated by ChatGPT/GPT‐4/Cursor against prevalent High‐Level Synthesis or hand‐coded HDL designs. Consequently, a novel design workflow is proposed and the constraints of using GPT, particularly in AI accelerators, are highlighted. This paper tests the possibility of using the latest AI chatbot, ChatGPT (GPT‐4) to do hardware design on FPGAs using Natural Language as the entry point. It is validated that the usage of GPT‐4 can potentially increase the speed of doing the initial design. However, we also found that because the GPT‐4 is an AI trained for chatting specifically, instead of for hardware design, it does not understand the hardware design concept even if it can write Verilog HDL or VHDL. We also use 3 case studies to show the functionality and limitations of the GPT‐4, which are the mainstream accelerators for ResNet, MobileNet and a systolic array for general‐purpose CNN acceleration.