FPGA and ASIC realisation of EMD algorithm for real-time signal processing

• Published in: IET circuits, devices & systems Vol. 14; no. 6; pp. 741 - 749
• Main Authors: Das, Kaushik, Nath, Debanjali, Pradhan, Sambhu Nath
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.09.2020; John Wiley & Sons, Inc
• Subjects: Algorithms; application specific integrated circuit; Application specific integrated circuits; ASIC; Cadence Genus tool; Cadence Innovus tool; clock gating; Design; Digilentinc Basys 3 FPGA board; Digital signal processors; dynamic power reduction; EMD algorithm; empirical mode decomposition algorithm; Field programmable gate arrays; field‐programmable gate array; frequency 25.0 MHz; hardware description languages; hardware verification; Hilbert transforms; integrated circuit design; interpolation; Layouts; logic design; mathematics computing; Modules; moving average; power consumption reduction; Power management; real‐time signal processing; Research Article; sawtooth transform; semiconductor laboratory cell library; Signal processing; simulation phase; size 180.0 nm; smoothing module; Software; splines (mathematics); traditional cubic spline interpolation; Verilog‐HDL code; Xilinx Vivado; splines (mathematics); real-time signal processing; field programmable gate arrays; signal processing; mathematics computing; Digilentinc Basys 3 FPGA board; hardware description languages; Verilog-HDL code; field-programmable gate array; Cadence Innovus tool; moving average; Hilbert transforms; semiconductor laboratory cell library; ASIC; integrated circuit design; application specific integrated circuit; dynamic power reduction; smoothing module; sawtooth transform; empirical mode decomposition algorithm; clock gating; size 180.0 nm; Xilinx Vivado; simulation phase; interpolation; Cadence Genus tool; frequency 25.0 MHz; EMD algorithm; power consumption reduction; traditional cubic spline interpolation; hardware verification; application specific integrated circuits; logic design
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2019.0322

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm2. For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.