EDXY – A low cost congestion-aware routing algorithm for network-on-chips

• Published in: Journal of systems architecture Vol. 56; no. 7; pp. 256 - 264
• Main Authors: Lotfi-Kamran, P., Rahmani, A.M., Daneshtalab, M., Afzali-Kusha, A., Navabi, Z.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.07.2010; Elsevier Sequoia S.A
• Subjects: Adaptive; Adaptive algorithms; Algorithms; Alliances; Bursty traffic; Computer networks; Congestion; Dynamic XY; Dynamics; Failure; Hierarchies; Integrated circuits; Link failure tolerant; Links; Low latency routing; Network-on-chip; Non uniform traffic; Routing; Routing (telecommunications); Routing algorithm; Simulation; Studies; Traffic congestion; Low latency routing; Routing algorithm; Adaptive; Link failure tolerant; Network-on-chip; Non uniform traffic; Bursty traffic; Dynamic XY
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/j.sysarc.2010.05.002

In this paper, an adaptive routing algorithm for two-dimensional mesh network-on-chips (NoCs) is presented. The algorithm, which is based on Dynamic XY (DyXY), is called Enhanced Dynamic XY (EDXY). It is congestion-aware and more link failure tolerant compared to the DyXY algorithm. On contrary to the DyXY algorithm, it can avoid the congestion when routing from the current switch to the destination whose X position (Y position) is exactly one unit apart from the switch X position (Y position). This is achieved by adding two congestion wires (one in each direction) between each two cores which indicate the existence of congestion in a row (column). The same wires may be used to alarm a link failure in a row (column). These signals enable the routing algorithm to avoid these paths when there are other paths between the source and destination pair. To assess the latency of the proposed algorithm, uniform, transpose, hotspot, and realistic traffic profiles for packet injection are used. The simulation results reveal that EDXY can achieve lower latency compared to those of other adaptive routing algorithms across all workloads examined, with a 20% average and 30% maximum latency reduction on SPLASH-2 benchmarks running on a 49-core CMP. The area of the technique is about the same as those of the other routing algorithms.