Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories

• Published in: IEICE Transactions on Information and Systems Vol. E96.D; no. 9; pp. 1914 - 1925
• Main Authors: YONEDA, Tomohiro, IMAI, Masashi
• Format: Journal Article
• Language: English
• Published: The Institute of Electronics, Information and Communication Engineers 2013
• Subjects: fault diagnosis; mean time to failure; multiple processor system; network-on-chip; pair and swap
• ISSN: 0916-8532; 1745-1361; 1745-1361
• DOI: 10.1587/transinf.E96.D.1914

We propose a fault diagnosis and reconfiguration method based on the Pair and Swap scheme to improve the reliability and the MTTF (Mean Time To Failure) of network-on-chip based multiple processor systems where each processor core has its private memory. In the proposed scheme, two identical copies of a given task are executed on a pair of processor cores and the results are compared repeatedly in order to detect processor faults. If a fault is detected by mismatches, the fault is identified and isolated using a TMR (Triple Module Redundancy) and the system is reconfigured by the redundant processor cores. We propose that each task is quadruplicated and statically assigned to private memories so that each memory has only two different tasks. We evaluate the reliability of the proposed quadruplicated task allocation scheme in the viewpoint of MTTF. As a result, the MTTF of the proposed scheme is over 4.3 times longer than that of the duplicated task allocation scheme.