Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL

• Published in: The Journal of supercomputing Vol. 79; no. 9; pp. 9866 - 9888
• Main Authors: de Castro, Manuel, Osorio, Roberto R., Vilariño, David L., Gonzalez-Escribano, Arturo, Llanos, Diego R.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.06.2023; Springer Nature B.V
• Subjects: Accuracy; Algorithms; Compilers; Computer Science; Cost control; Data compression; Energy efficiency; Field programmable gate arrays; Hardware description languages; Interpreters; Motion simulation; Multimedia; Processor Architectures; Programming Languages; Reconfigurable hardware; Resource utilization; Software; Video compression; Video coding; OpenCL; Motion estimation; FPGA
• ISSN: 0920-8542; 1573-0484; 1573-0484
• DOI: 10.1007/s11227-023-05051-3

Motion Estimation is one of the main tasks behind any video encoder. It is a computationally costly task; therefore, it is usually delegated to specific or reconfigurable hardware, such as FPGAs. Over the years, multiple FPGA implementations have been developed, mainly using hardware description languages such as Verilog or VHDL. Since programming using hardware description languages is a complex task, it is desirable to use higher-level languages to develop FPGA applications.The aim of this work is to evaluate OpenCL, in terms of expressiveness, as a tool for developing this kind of FPGA applications. To do so, we present and evaluate a parallel implementation of the Block Matching Motion Estimation process using OpenCL for Intel FPGAs, usable and tested on an Intel Stratix 10 FPGA. The implementation efficiently processes Full HD frames completely inside the FPGA. In this work, we show the resource utilization when synthesizing the code on an Intel Stratix 10 FPGA, as well as a performance comparison with multiple CPU implementations with varying levels of optimization and vectorization capabilities. We also compare the proposed OpenCL implementation, in terms of resource utilization and performance, with estimations obtained from an equivalent VHDL implementation.