Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective

• Published in: Proceedings of the IEEE Vol. 98; no. 2; pp. 160 - 190
• Main Authors: Gupta, Sumeet Kumar, Raychowdhury, Arijit, Roy, Kaushik
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive beta ratio modulation; Circuits; Degradation; Design optimization; Devices; Digital; Digital circuits; double gate MOSFETs; Electric potential; Energy dissipation; Logic; Logic circuits; Logic design; Logic devices; low-voltage design; parallelization and pipelining; parameter variations; Power supplies; Robustness; SRAM; steep devices; subthreshold logic; Threshold voltage; Voltage
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2009.2035060

Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.