Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

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Bibliographic Details
Published inIEICE electronics express
Format Journal Article
LanguageEnglish
Published 2016
Online AccessGet full text
ISSN1349-9467
1349-2543
1349-9467
DOI10.1587/elex.13.20160641

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ISSN:1349-9467
1349-2543
1349-9467
DOI:10.1587/elex.13.20160641