An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic...

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Bibliographic Details
Published inJournal of semiconductors Vol. 31; no. 6; pp. 142 - 145
Main Author 刘鸣 陈虹 李长猛 王志华
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.06.2010
Subjects
CMOS工艺
SRAM
亚阈值
单元测试
工作电压
核武器
纳米
超低功耗
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ISSN1674-4926
DOI10.1088/1674-4926/31/6/065013

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Summary:This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.
Bibliography:TN929.11
sub-threshold SRAM 11T SRAM cell ultra-low-power SoC
TP333
11-5781/TN
ISSN:1674-4926
DOI:10.1088/1674-4926/31/6/065013