A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 2; pp. 223 - 234
• Main Authors: Liu, Yifang, Hu, Jiang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; circuit optimization; Circuits; Combinatorial analysis; Delay estimation; Dynamic programming; Gates (circuits); Heuristic; Iterative algorithms; Linear programming; Mathematical models; Optimization methods; Power dissipation; Sizing; Table lookup; Threshold voltage; Time measurements; Timing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2009.2035575

Gate sizing and threshold voltage (V t ) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optima and the discretization may be subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and V t assignment. The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search. The process of joint relaxation and restriction is conducted iteratively to systematically improve solutions. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 22% less power dissipation subject to the same timing constraints.