Configuration relocation and defragmentation for run-time reconfigurable computing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 10; no. 3; pp. 209 - 220
• Main Authors: Compton, K., Zhiyuan Li, Cooley, J., Knol, S., Hauck, S.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.2002; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Applied sciences; Computation; Computer applications; Computers, microcomputers; Costs; Electronics; Exact sciences and technology; Field programmable gate arrays; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Microprocessors; Power system management; Reconfigurable architectures; Reconfigurable hardware; Reconfiguration; Relocation; Run time (computers); Runtime; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software algorithms; Very large scale integration; System architecture; VLSI circuit; Programming; Field programmable gate array; Computing; Software tool; Experimental result; Algorithm performance; System performance; Integrated circuit; Reconfigurable architectures; Fast algorithm; Comparative study
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2002.1043324

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. By mapping the compute-intensive sections of an application to reconfigurable hardware, custom computing systems exhibit significant speedups over traditional microprocessors. However, this potential acceleration is limited by the requirement that the speedups provided must outweigh the considerable cost of reconfiguration. The ability to relocate and defragment configurations on field programmable gate arrays (FPGAs) can dramatically decrease the overall reconfiguration overhead incurred by the use of the reconfigurable hardware. We therefore present hardware solutions to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA, as well as software algorithms for controlling this hardware. This results in factors of 8 to 12 improvement in the configuration overheads displayed by traditional serially programmed FPGAs.