Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

• Published in: Journal of low power electronics and applications Vol. 13; no. 1; p. 2
• Main Authors: Barbirotta, Marcello, Cheikh, Abdallah, Mastrandrea, Antonio, Menichelli, Francesco, Ottavi, Marco, Olivieri, Mauro
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.03.2023
• Subjects: Analysis; Architecture; Central processing units; Circuit protection; Computer architecture; Cost control; Error correction & detection; Fault tolerance; fault-detection; fault-injection; Human resource management; Interleaved-Multi-Threading (IMT); Logic; Microprocessors; Multiprocessing; Redundancy; RISC; RISC-V; Semiconductor industry; Single event upsets; Software; United States
• ISSN: 2079-9268; 2079-9268
• DOI: 10.3390/jlpea13010002

Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign.