Low-Power SAR ADCs: Basic Techniques and Trends
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architectur...
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| Published in | IEEE open journal of solid-state circuits Vol. 2; p. 1 |
|---|---|
| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
New York
IEEE
2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects | |
| Online Access | Get full text |
| ISSN | 2644-1349 2644-1349 |
| DOI | 10.1109/OJSSCS.2022.3211482 |
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| Abstract | With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Further, the limitations of SAR ADCs are outlined and hybrid architecture trends, like noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples. |
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| AbstractList | With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples. With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Further, the limitations of SAR ADCs are outlined and hybrid architecture trends, like noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples. |
| Author | Harpe, Pieter |
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| SubjectTerms | Analog to digital converters Analog-digital conversion Analog-to-Digital Converter Analog-to-digital converter (ADC) Capacitors Distortion Latches Linearity Low-Power Noise-Shaping Power demand Power efficiency Power management Registers Successive Approximation Switched-Capacitor Circuit Trends |
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| Title | Low-Power SAR ADCs: Basic Techniques and Trends |
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