Low-Power SAR ADCs: Basic Techniques and Trends

With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architectur...

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Bibliographic Details
Published inIEEE open journal of solid-state circuits Vol. 2; p. 1
Main Author Harpe, Pieter
Format Journal Article
LanguageEnglish
Published New York IEEE 2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Analog to digital converters
Analog-digital conversion
Analog-to-Digital Converter
Analog-to-digital converter (ADC)
Capacitors
Distortion
Latches
Linearity
Low-Power
Noise-Shaping
Power demand
Power efficiency
Power management
Registers
Successive Approximation
Switched-Capacitor Circuit
Trends
Online AccessGet full text
ISSN2644-1349
2644-1349
DOI10.1109/OJSSCS.2022.3211482

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Summary:With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For Analog-to-Digital-Converters (ADCs), the Successive Approximation Register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Further, the limitations of SAR ADCs are outlined and hybrid architecture trends, like noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples.
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ISSN:2644-1349
2644-1349
DOI:10.1109/OJSSCS.2022.3211482