Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorith...

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Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 18; no. 7; pp. 1014 - 1025
Main Authors Chung-Ping Chen, Chu, C.C.N., Wong, D.F.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.07.1999
Institute of Electrical and Electronics Engineers
Subjects
Algorithms
Applied sciences
Circuit optimization
Circuits
Delay
Delay effects
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Gates (circuits)
Integrated circuit interconnections
Integrated circuit technology
Integrated circuits
Iterative algorithms
Lagrangian functions
Large-scale systems
Optimization
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sizing
Very large scale integration
Wire
Performance evaluation
Relaxation
VLSI circuit
Circuit design
Interconnection
Optimal solution
Iterative method
Elmore delay
Fast algorithm
Lagrangian method
Optimization
Online AccessGet full text
ISSN0278-0070
DOI10.1109/43.771182

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Summary:This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g., minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and "one-gate/wire-at-a-time" greedy optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 27648 gates and wires in 11.53 min using under 23 Mbytes memory on a PC with a 333-MHz Pentium II processor.
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ISSN:0278-0070
DOI:10.1109/43.771182