Front-end electronics for PWO-based PHOS calorimeter of ALICE

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Vol. 567; no. 1; pp. 264 - 267
• Main Authors: Muller, Hans, Budnikov, Dmitry, Ippolitov, Mikhail, Li, Qingxia, Manko, Vladislav, Pimenta, Rui, Rohrich, Dieter, Sibiryak, Iouri, Skaali, Bernhard, Vinogradov, Alexandre
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.11.2006
• Subjects: APD; APD gain calibration; Electromagnetic calorimeter; Embedded electronics packaging; Energy resolution; Fast-OR; FEE electronics; PWO; RMS noise; Shaping time; Timing resolution; Trigger-electronics; APD gain calibration; Shaping time; PWO; Trigger-electronics; Electromagnetic calorimeter; 85.60.Dw; 85.60.Gz; Embedded electronics packaging; 29.40.Vj; 42.66.Lc; Timing resolution; Fast-OR; APD; Energy resolution; RMS noise; FEE electronics
• ISSN: 0168-9002; 1872-9576
• DOI: 10.1016/j.nima.2006.05.104

The electromagnetic Photon Spectrometer (PHOS) of ALICE consists of five modules with 56×64 PWO crystals, operated at −25 °C. Glued to each crystal are APD diodes which amplify a lightyield of 4.4 photoelectrons/MeV, followed by charge-sensitive pre-amplifiers with a charge conversion gain of ca. 1 V/pC. We describe our new 32-channel shaper/digitizer and readout electronics for gain-programmable photodiodes. These Front-End Electronics (FEE) cards are installed below the crystals in an isolated warm volume in geometrical correspondence to 2×16 crystal rows per card. With a total detector capacitance of 100 pF and a noise level of 3 MeV, the FEEs cover a 14 bit dynamic range from 5 MeV to 80 GeV. The low noise level is achieved by operating the APDs and preamplifiers at low temperature and by applying a relatively long shaping time of 1 μs. The offline timing resolution, obtained via a Gamma-2 fit is less than 2 ns. The second-order, dual-gain shapers produce semi-Gaussian output for 10 bit ADCs with embedded multi-event buffers. A Readout Control Unit (RCU) masters data readout with address-mapped access to the event-buffers and controls registers via a custom bus which interconnects up to 14 FEE cards. Programmable bias voltage controllers on the FEE cards allow for very precise gain adjustment of each individual APD. Being co-designed with the TRU trigger cards, each FEE card generates eight fast signal sums (2×2 crystals) as input to the TRU. FPGA-based algorithms generate level-0 and level-1 trigger decisions at 40 MHz and allow PHOS also to operate in self-triggered mode. Inside each PHOS module there are 112 FEE and 8 TRU cards which dissipate ca. 1 kW heat which is extracted via a water cooling system.