A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degree for the 40, 80...

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Bibliographic Details
Published inJournal of instrumentation Vol. 7; no. 12; p. C12014
Main Authors Poltorak, K, Tavernier, F, Moreira, P
Format Journal Article
LanguageEnglish
Published 01.12.2012
Subjects
Clocks
CMOS
Electric potential
Frequency multipliers
Instrumentation
Multiplication
Voltage
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ISSN1748-0221
1748-0221
DOI10.1088/1748-0221/7/12/C12014

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Summary:A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320 MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90 degree for the 40, 80 and 160 MHz output and 22.5 degree for the 320 MHz output. The radiation-hard design, integrated in a 130 nm CMOS technology, is able to operate at a supply voltage between 1.2 V and 1.5 V.
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ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/7/12/C12014