A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 11; pp. 2487 - 2496
• Main Authors: Chung, Ching-Che, Sheng, Duo, Li, Chang-Jun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital duty-cycle corrector (ADDCC); Clocks; CMOS; Delay lines; delay-locked loop (DLL); Delays; Design engineering; digitally controlled delay line; High speed; Logic gates; phase alignment; Power consumption; Sampling; Semiconductors; System-on-chip; Time delay; Tuning; Very large scale integration; wide-range; digitally controlled delay line; delay-locked loop (DLL); All-digital duty-cycle corrector (ADDCC); phase alignment; wide-range
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2370631

A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double sampling analog-to-digital converters. In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to reduce the required length of the delay line to half of the input clock period. Thus, it can extend the operating frequency toward a lower frequency with small area cost as compared with the conventional design. The proposed design is implemented in a standard performance 90-nm CMOS process, and the active area is 170 × 170 μm 2 . The input frequency of the proposed ADDCC ranges from 75 to 734 MHz, and the input duty-cycle ranges from 9% to 86%. The measured output duty-cycle error is less than 1.78%. The proposed ADDCC consumes 4.59 mW at 734 MHz and 0.9 mW at 75 MHz with a 1.0-V power supply.